| 摘要 |
FIELD: computer engineering, possible use in addition devices. ^ SUBSTANCE: in accordance to the method, at first clock period the code of second summand is received in triggers of second summand and code of first summand, which is shifted for one bit to the right by code of total of previous addition output and stored in triggers of first summand, is shifted one bit to the left, at second clock period code of total is formed with consideration of transition at each bit, at third clock period the code of total is outputted to information outputs of device, resulting total is shifted one bit to the right with memorization of the first summand in triggers. Device contains AND elements, OR elements, NOT elements, RS-triggers, control inputs. ^ EFFECT: simplification of device, expanded functional capabilities, increased speed of operation. ^ 2 cl, 1 dwg |
