CLOCK GENERATION CIRCUIT CONTRO METHOD OF CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

摘要

A clock duty adjusting circuit is provided in the subsequent stage of a variable delay circuit to control the delay of the variable delay circuit with the rising edge of clock. When the phase of the rising edge is matched with the reference clock, the duty of output clock is matched with the duty of the reference clock by adjusting the pulse width of the signal with the duty adjusting circuit at the falling edge.