| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress the influence of two synchronous output signals output by a shift register circuit. <P>SOLUTION: The shift register circuit is provided with a transistor Q1 between a gate line output terminal OUT and a clock terminal CK, a transistor Q2 between the gate line output terminal OUT and a first power supply terminal s1, a transistor Q1D between a carry signal output terminal OUTD and the clock terminal CK, and a transistor Q2D between the carry signal output terminal OUTD and the first power supply terminal s1. Gates of the transistors Q2 and Q2D are connected each other. Also, gates of the transistor Q3 connected between the gate of the transistor Q1 and the second power supply terminal s2 and the transistor Q3D connected between the gate of the transistor Q1D and the second power supply terminal s2 are connected together to an input terminal IN. <P>COPYRIGHT: (C)2008,JPO&INPIT |
