| 摘要 |
PROBLEM TO BE SOLVED: To reduce the circuit scale, to improve the reliability, to increase the response speed, and to reduce through-current. SOLUTION: When an input signal IN becomes H level; an input signal IN2 delayed by a delay timeτD by a delay element 21 is generated, L level of signals A and B is generated, and thereby NMOSs 53 and 54 are turned off simultaneously for a duration of the delay timeτD. During this time, a signal C generated from the signals A and B becomes H level, and a signal C3 output from a simple level shift portion 40 changes to H level (VDD2), turning on NMOS 55. As a result, charges move in output nodes N51 and N52 on both sides of a main level shift 50, and the potential rises on the drain side of NMOS 54 while lowering the potential on the drain side of NMOS 53. When NMOS 53 is turned on after the passage of the delay timeτD; the potential on the drain side of NMOS 54 has already risen to a certain level of potential, and therefore the ability of PMOS 51 has decreased and the potential on the drain side of NMOS 53 rapidly decreases to 0 V. COPYRIGHT: (C)2008,JPO&INPIT
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