发明名称 |
Disparate clock domain synchronization |
摘要 |
Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
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申请公布号 |
US2007230509(A1) |
申请公布日期 |
2007.10.04 |
申请号 |
US20060396305 |
申请日期 |
2006.03.31 |
申请人 |
TO HING THOMAS Y;LEMOS GREGORY |
发明人 |
TO HING (THOMAS) Y.;LEMOS GREGORY |
分类号 |
H04J3/06 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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