发明名称 System and shadow circuits with output joining circuit
摘要 In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.
申请公布号 US7278074(B2) 申请公布日期 2007.10.02
申请号 US20050044826 申请日期 2005.01.26
申请人 INTEL CORPORATION 发明人 MITRA SUBHASISH;ZHANG MING;MAK TAK M.;SHI QUAN;KIM KEE SUP
分类号 G01R31/28 主分类号 G01R31/28
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