| 摘要 |
A clock buffer circuit of a semiconductor memory device is provided to achieve low power consumption of the device by reducing an output current in a power down mode of the semiconductor memory device. A differential amplifier part(150) amplifies a clock signal differentially and then buffers the clock signal. An enable part(110) generates a buffer enable signal controlling the operation of the differential amplifier part, and disables the differential amplifier part by disabling the buffer enable signal in a power down mode of a semiconductor device in response to the input of at least one control signal. The control signal includes an inverted clock enable signal, a self refresh signal and RAS idle signals.
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