| 摘要 |
<p>A nonvolatile semiconductor storage device having a small memory cell area and can perform highly accurate high-speed operation. Diffusion layers (2a, 2b) are formed in honeycomb shape and are arranged by being shifted by a quarter pitch, and at a section where ODD_WL0 and WL1 intersect the diffusion layer (2a) and a section where EVEN_WL0 and WL1 intersect the diffusion layer (2b), a memory transistor (MemoryTr) and a select transistor (SelectTr) are formed. At that time, the memory transistor and the select transistor are arranged so that memory cells (E1, E2) are formed between ODD_BL0 and BL1 connected to each of the diffusion layers (2a, 2b), and memory cells (E3, E4) are formed between EVEN_BL0 and BL1. Thus, even when the select transistor is provided, a multitude of memory cells can be arranged in array in a small layout area.</p> |
