| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transfer controller for dividing and transferring a mass of large capacity data without increasing the management time of the data transfer controller by an MPU without excessively increasing the time occupied by a specified bus master. SOLUTION: The data transfer controller is equipped with a transfer origin address register for storing a transfer origin address, a transfer destination address register for storing a transfer destination address, a transfer count register for storing the count of data transfer, and a maximum transfer count setting register for storing the maximum data transfer count setting value per block. The data corresponding to the data transfer count stored in the transfer count register are transferred by each of the maximum transfer count setting value stored in the maximum transfer count setting value register. COPYRIGHT: (C)2007,JPO&INPIT
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