| 摘要 |
The present invention discloses a PLL ( 90 ), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector ( 92 ) adapted to output a phase error ( 152 ), a vertical sync discrete time oscillator (DTO) block ( 98 ) adapted to output a vertical sync DTO ( 130 ) based on the phase error ( 152 ), and an output logic ( 100 ) adapted to detect a vertical sync based on the vertical sync DTO ( 130 ).
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