VERTICAL GATED ACCESS TRANSISTOR

摘要

According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches (400) and a plurality of shallow trenches (404) in a first region (308) of a substrate (110). At least one of the shallow trenches (404) is positioned between two deep trenches (400). The plurality of shallow trenches (404) and the plurality of deep trenches (400) are parallel to each other. The method further comprises depositing a layer of conductive material (454) over the first region (308) and a second region (310) of the substrate (110). The method further comprises etching the layer of conductive material (454) to define a plurality of lines (470) separated by a plurality of gaps over the first region (308) of the substrate, and a plurality of active device elements (460) over the second region (310) of the substrate (110). The method further comprises masking the second region (310) of the substrate (110). The method further comprises removing the plurality of lines (470) from the first region (308) of the substrate (110), thereby creating a plurality of exposed areas (476) from which the plurality of lines (470) were removed. The method further comprises etching a plurality of elongate trenches (476) in the plurality of exposed areas (476) while the second region (310) of the substrate (110) is masked.