| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that there are many cases that in integrating a fault detection circuit in a register in the arbitrary logic part of a logic circuit, a method for manually designing a circuit, or for uniformly adding the fault detection circuit to the regular section of the logic circuit may result in the redesign of the logic circuit due to the violation of delay constraint after the addition of the fault detection circuit. SOLUTION: A fault detection circuit having a delay value between the registers of a logic circuit and a delay value which falls within the extent of delay margin to be calculated from delay constraint applied to the logic circuit is generated, and added to the logic circuit. COPYRIGHT: (C)2007,JPO&INPIT
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