| 摘要 |
A first gate of a multi-gate transistor within a pass gate can be provided with a bias voltage to alter the bias point of the multi-gate transistor. The bias point can be controlled differently during different phases of memory cell operation and the bias point can provide operational improvements during each phase of memory cell operation. In a specific configuration the multi-gate semiconductor device has a first current electrode connected to a first node of a bit cell, a second current electrode connected to a bit line, and a second gate electrode connected to a read/write line, wherein the control module can alter the bias point of the multi-gate semiconductor differently during different phases of memory cell operation. In one embodiment a FinFET can be connected in a parallel configuration with the multi-gate transistor.
|
