| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To obtain a frequency multiplier circuit for multiplying a desired clock signal by 2 in electronics, and a transmitter performing CMI encoding of transmission information in synchronism with a clock signal multiplied by 2 generated from the frequency multiplier circuit in which the clock signal multiplied by 2 can be generated precisely and inexpensively with small physical size. <P>SOLUTION: The frequency multiplier circuit comprises a delay means for generating a delay clock signal by imparting a delay d(=T/2) corresponding to one half of the period T of a clock signal to the clock signal, and a pulse width regulation means for generating a train of pulse signals having a pulse width equal to a quarter of the period T by synchronizing with the leading edge or the training edge of both the clock signal and the delay clock signal. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
