METHOD FOR ENHANCING YIELD OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE AND SYSTEM FOR THE SAME

摘要

A method and a system for improving yield of a semiconductor integrated circuit device are provided to design a yield-maximized layout by using a fault rate of a calculated design rule to correct a layout of interest. A plurality of experimental design rule values with respect to a design rule are determined(S20). A fault rate of each experimental design rule value is measured(S30). The number of features corresponding to the respective experimental design rule values are counted within a layout of interest(S40). A fault rate of the design rule is provided by using the fault rate of the experimental design rule and the number of features(S50). The layout of interest is corrected by using the fault rate of the design rule(S70). The design rule out of the plurality of design rules is a critical factor with respect to yield.