Nonvolatile semiconductor memory device that achieves speedup in read operation

摘要

A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes "H" for a predetermined period of time after read data is obtained during a read period.