| 摘要 |
A stereo modulator converts an inputted audio signal to a stereo composite signal. A frequency modulator, which includes a PLL circuit, performs frequency modulation with the stereo composite signal outputted from the stereo modulator as being a modulation signal. A first programmable divider and a second programmable divider divide an external clock signal inputted from the outside by a first division ratio and a second division ratio set respectively and outputs. A first clock signal outputted from the first programmable divider is used as a reference clock signal for generating the stereo composite signal, and a second clock signal outputted from the second programmable divider is used as a reference clock signal of the PLL circuit.
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