SINGLE-CYCLE LOW-POWER CPU ARCHITECTURE

摘要

An n architecture for implementing an instruction pipeline within a CPU comprises an arithmetic logic unit (ALU) (210) , an address arithmetic unit (AAU) (215) , a program counter (PC) (220) , a read¬ only memory (ROM) (230) coupled to the program counter (220) , to an instruction register (240) , and to an instruction decoder (250) coupled to the arithmetic logic unit (210) . A random access memory (RAM) (270) is coupled to the instruction decoder (250) , to the arithmetic logic unit (210) , and to a RAM address register (260) .