| 摘要 |
PROBLEM TO BE SOLVED: To provide an apparatus for handling data cache misses out-of-order for a plurality of asynchronous pipelines. SOLUTION: This apparatus associates a load tag (LTAG) identifier with a load instruction, and constantly monitors load instructions across multiple pipelines as indexes to the load table data structure of the load target buffer. The load table manages the cache hits/misses, and is used to aid in the recycling of data from the L2 cache. When the load instruction is issued and the corresponding entry in the load table is seen as what is marked as "miss", the effects of issuance of the load instruction are canceled. The load instruction is stored in the load table for future reissuing to the instruction pipe line when the requested data is recycled. COPYRIGHT: (C)2007,JPO&INPIT
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