| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a CPU for achieving a reset function without requiring any reset exclusive logic. <P>SOLUTION: This CPU 10 is provided with a fetch circuit 20 for reading an instruction code 32, and for fetching it to a fetch register 30 and an instruction decoding execution circuit 40 for receiving the instruction code fetched to the fetch register 30, and for decoding and executing it. The fetch register 30 is configured so that a reset input can be connected to a reset signal 80, and initialized into a predetermined software interrupting instruction during reset. An instruction decoding execution circuit 40 includes a software interruption processing part 50 for decoding and executing the instruction code of the predetermined software interrupting instruction. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
