发明名称 |
Data memory address generation for time-slot interchange switches |
摘要 |
Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.
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申请公布号 |
US7257115(B2) |
申请公布日期 |
2007.08.14 |
申请号 |
US20020205177 |
申请日期 |
2002.07.25 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
MATTHEWS FRANK;MACADAM DAVE |
分类号 |
H04L12/50;G11C7/10;G11C8/06;G11C8/18 |
主分类号 |
H04L12/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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