发明名称 Method and apparatus of evaluating layer matching deviation based on CAD information
摘要 An apparatus of evaluating a layer matching deviation based on CAD information of the invention, is provided with means for storing CAD data and a function of displaying to overlap a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a design CAD image read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying to overlap a pattern image of the semiconductor device formed on the wafer and the design CAD image of the pattern, in addition thereto, a function capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern formed at a later step by displaying to overlap a design CAD image of the pattern formed at the later step.
申请公布号 US7257785(B2) 申请公布日期 2007.08.14
申请号 US20040823104 申请日期 2004.04.13
申请人 SII NANOTECHNOLOGY INC. 发明人 MATSUOKA RYOICHI
分类号 G06F17/50;H01L21/66;G03F7/20;G03F9/00;G06T1/00;G06T3/00;G06T5/20;H01L21/027 主分类号 G06F17/50
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