| 摘要 |
A system having a bus architecture for improving CPU performance and a performing improving method thereof are provided to improve the CPU performance by permitting the second master not to keep a hold state when the second master accesses a memory device connected to a local bus through a local bus even if the first master such as DMA(Direct Memory Access) has right for a main bus. The second local bus(225) is connected between the main bus(219) connected to a peripheral(223) and the memory device connected to the first local bus(217). The first/second master(201,221) respectively has the right for the main bus to access the peripheral or has the right for the first/second local bus to access the memory device. The second master is connected to the main bus. A bridge(203) is connected to the main bus, the first master, and the memory device, monitors whether the right for the main bus is given to the second master, and decodes an address output from the first master. The bridge outputs the first waiting signal to the first master, or outputs the address to the memory device or the peripheral based on a monitoring and decoding result.
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