发明名称 SYSTEM BUS CONTROLLER, INTEGRATED CIRCUIT, AND DATA PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a system bus controller capable of effectively utilizing a system bus as much as possible and efficiently transferring data. SOLUTION: The system bus controller includes; the system bus being a path of data transferred from a bus master; a bus condition monitor part for monitoring a busy or idle state of the system bus; a bus assignment part for assigning a bus width permitted for transfer to the bus master on the basis of the busy or idle state of the system bus monitored by the bus condition monitor part, in response to a transfer request from the bus master; and a bus width varying part for varying a bus width for data transfer of the bus master in accordance with the assigned bus width. Since the bus width for data transfer is varied in accordance with the bus width permitted for use, the transfer request is not made to wait. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007200245(A) 申请公布日期 2007.08.09
申请号 JP20060021115 申请日期 2006.01.30
申请人 SHARP CORP 发明人 IRISA NAOKI
分类号 G06F13/36 主分类号 G06F13/36
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