发明名称 TEST PATTERN AND METHOD FOR MEASURING SILICON ETCHING DEPTH
摘要 Embodiments of a test pattern and a method for measuring silicon etching depth are provided. After a contact-hole forming process, an optical critical dimension (OCD) is measured with respect to a test pattern formed on a semiconductor chip, so that the silicon etching depth may be analyzed in real time. Critical dimensions of contact holes in the actual working cells of the semiconductor circuit would then coincide with the OCD measurement of the contact holes of the test pattern. Consequently, etching conditions for forming a contact hole may be controlled in real time, and thus a yield of a semiconductor can be effectively improved.
申请公布号 US2007184565(A1) 申请公布日期 2007.08.09
申请号 US20060566637 申请日期 2006.12.04
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 PARK HWAN-SHIK;KIM SUNG-GON;JUN CHUNG-SAM;KIM KYE-WEON;PARK JANG-IK;SONG WON-KWAN
分类号 H01L21/66 主分类号 H01L21/66
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