| 摘要 |
A clock and data recovery circuit is provided to enable duty correction individual and corresponding to duty variation of even and odd data, by using a clock signal interpolated by a plurality of interpolators in detecting input data and edges. A plurality of interpolators(301,302) generates a clock signal of a phase formed by interpolating phase difference of two input clock signals. A circuit receives a clock signal of a first set comprising a plurality of clock signals output from the interpolators, and generates a clock signal of a second set obtained by dividing the phase of clock signals with adjacent phase among the clock signal of the first set. The clock signal of the first set is used in detecting input data and one side of edge, and the clock signal of the second set is used in detecting the input data and the other side of the edge.
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