发明名称 Cache memory observation device and method of analyzing processor
摘要 A cache miss judger judges a cache miss when a cache access is executed. An entry region judger judges which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses using at least a part of an index for selecting an arbitrary cache line in the cache memory. A cache miss counter counts number of the cache misses judged by the cache miss judger in each of the entry regions that is made to correspond to each of the cache accesses.
申请公布号 US2007180192(A1) 申请公布日期 2007.08.02
申请号 US20070700065 申请日期 2007.01.31
申请人 发明人 MATSUDA GENICHIRO
分类号 G06F12/00 主分类号 G06F12/00
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