发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technology capable of shortening the manufacturing TAT of a power MOSFET having a groove structure and a low ON-state resistance. SOLUTION: After a gate groove 9 is provided on an epitaxial layer 2 using a dry-etching device, the gate groove 9 is successively subjected to a thermal treatment in a vacuum using the dry-etching device that has been used for its formation, whereby silicon atoms located on the side faces of the gate groove 9 are rearranged to make the side faces of the gate groove 9 smooth. By this setup, round etching usually carried out for the rearrangement of silicon atoms to smooth the side faces of the gate groove 9 by means of ion bombardment can be dispensed with. Therefore, the side faces of the gate groove 9 become smooth, so that the ON-state resistance of the power MOSFET can be reduced, and furthermore a round etching process can be dispensed with, whereby the manufacturing TAT of the power MOSFET can be shortened. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007194380(A) 申请公布日期 2007.08.02
申请号 JP20060010559 申请日期 2006.01.19
申请人 RENESAS TECHNOLOGY CORP 发明人 HASHIZUME YUJI
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
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