发明名称 |
MEMORY CELL HAVING STRESSED LAYERS |
摘要 |
A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and suicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell. |
申请公布号 |
WO2007070664(A3) |
申请公布日期 |
2007.08.02 |
申请号 |
WO2006US47831 |
申请日期 |
2006.12.13 |
申请人 |
APPLIED MATERIALS;ARGHAVANI, REZA;YEH, ELLIE;M'SAAD, HICHEM |
发明人 |
ARGHAVANI, REZA;YEH, ELLIE;M'SAAD, HICHEM |
分类号 |
H01L21/336;H01L21/8239;H01L27/105;H01L29/788 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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