| 摘要 |
PROBLEM TO BE SOLVED: To provide a level shift circuit of a single end output type in which an increase in a delay time involved in a voltage level shift operation during a low voltage is suppressed and an increase in an occupied area of the circuit is also suppressed. SOLUTION: The level shift circuit is constituted by using a CMOS, wherein first and second inverters (300, 200) are provided of such a type that gates of MOS transistors are individually driven, and the first inverter (300) is used as a level conversion means. A voltage level of a first control signal (CS1) output from an output point (no1) of the first inverter 300 is forcibly reduced by a voltage drop circuit (CONT1), the operation of the second inverter 200 is quickened, and level inversion of an output signal in the first inverter 300 is accelerated as a result. Furthermore, current capabilities of the transistors are optimally balanced, and an increase in the circuit area is suppressed by reducing, in particular, the size of the transistor constituting the second inverter (200). COPYRIGHT: (C)2007,JPO&INPIT
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