发明名称 Method of Leakage Optimization in Integrated Circuit Design
摘要 This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells, identifies corresponding candidate cells having the same function and swaps a candidate design cell having a least leakage current for the design cell.
申请公布号 US2007180415(A1) 申请公布日期 2007.08.02
申请号 US20070619341 申请日期 2007.01.03
申请人 PUNDOOR SHRIKRISHNA 发明人 PUNDOOR SHRIKRISHNA
分类号 G06F17/50 主分类号 G06F17/50
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