| 摘要 |
A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.
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