| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory array-testing circuit which realizes latency-time control. SOLUTION: When a defective memory cell of a memory cell array 100 is detected, a comparator 104 makes a fault-signal output line 108 generate a fault signal. The fault signal is sent to a shift register 112, and an output circuit block 118 enters a high-impedance condition in accordance with the fault signal. The shift register 112 includes a lot of latches which conform to variations in latency time, for example, 1, 2 or 3 clock cycles. COPYRIGHT: (C)2007,JPO&INPIT |
