| 摘要 |
The present invention provides ESD protection circuits. The circuit includes: a resistor, a capacitance, a first transistor, an inverter set, and a second transistor. The resistor is connected between a first voltage and node N 1 . The capacitor is connected between node N 1 and a second voltage. The first transistor has a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and a third terminal coupled to node N 2 . The inverter set has an input terminal coupled to node N 1 and an output terminal coupled to node N 2 . The second transistor has a first terminal coupled to a first inverter of the inverter set, a second terminal coupled to the second voltage, and a third terminal coupled to an output terminal of a second inverter of the inverter set. The output terminals of the first and the second inverters correspond to opposite logic levels.
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