| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit having improved timing convergence by suppressing skew caused by dispersion in-chip transmission paths for a reference clock and a frequency division clock. <P>SOLUTION: The clock generating circuit includes, a first circuit 10, a second circuit 20A, and a third circuit 50A. The first circuit 10 generates a first clock signal s10. The second circuit 20A divides the frequency of the first clock signal s10 to produce a second clock signal s20. The third circuit 50A produces a third clock signal s50 which has a period of the second clock signal s20 and in which a timing of change from a first logic level to a second logic level is the same as the corresponding timing of the first clock signal s10 from the first and second clock signals s10, s20. <P>COPYRIGHT: (C)2007,JPO&INPIT |
