| 摘要 |
A PMOS transistor and a forming method thereof are provided to improve off-leakage current increase, operation voltage damage, and operation speed lowering due to HEIP(Hot Electron Induced Punch through) phenomenon by forming a smaller gate tap at a boundary region of an active region and an isolation layer. A semiconductor substrate(30) is defined by an isolation layer. The semiconductor substrate has an active region(31) whose both sides among channel expectation regions in a channel width direction are recessed. A gate(33) is formed on the active region including the recessed region. The gate has a tap(33') at a boundary region of the active region and the isolation layer. Source/drain regions(35a,35b) are formed in the active region at both sides of the gate. A sum of two times of the depth of the recessed active region and the length thereof is 3000-5000 A.
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