| 摘要 |
The proposed computing system contains a processor and peripheral devices connected by a common bus. Each peripheral device contains an interrupt signal former, an OR logic element, a trigger, and an AND logic element. The corresponding output of the interrupt signal former of each peripheral device is connected to the signal input of the trigger of the following peripheral device. The corresponding output of the interrupt signal former of the last peripheral device is connected to the signal input of the trigger of the first peripheral device.
|
