| 摘要 |
An internal reset signal generator that generates an internal reset disable signal after an internal high voltage device has been completely reset. This can substantially reduce errors in operation of semiconductor memory devices. A first circuit generates a first control signal until the power source voltage reaches a stabilized state and a second control signal thereafter. A delay circuit responds to the first and second control signals and a reset complete signal from a reset circuit, and generates an internal reset disable signal only when the second control signal and the reset completion signal are inputted simultaneously, and in other cases, generates an internal reset signal. A reset circuit is connected in a feedback circuit with the delay circuit. It resets a high-voltage device in response to the internal reset signal, and generates a reset completion signal when the high voltage device is reset.
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