Semiconductor memory device e.g. dynamic RAM, has each unit memory cell comprising complementary floating body transistor capacitor-less memory cells

摘要

A memory cell array has several unit memory cells and each of the unit memory cell comprises complementary floating body transistor capacitor-less memory cells. Several complementary bit line pairs connected to the complementary floating body transistor capacitor-less memory cells. A logic value of each unit memory cell is defined by a difference in the threshold voltages of the complementary floating body transistor capacitor-less memory cells. Independent claims are also included for the following: (1) data writing method in a semiconductor memory device; and (2) data reading method in a semiconductor memory device.