发明名称 Fully-buffered dual in-line memory module with fault correction
摘要 A memory system comprises first memory that includes memory cells that are selectively refreshed at a refresh rate. A test module tests operation of the memory cells at the refresh rate and that identifies T of the memory cells that are inoperable when refreshed at the refresh rate, where T is an integer greater than zero. Content addressable memory (CAM) includes D CAM memory cells where D is an integer greater than or equal to one. An adaptive refresh module selectively adjusts a refresh rate of the first memory based on T and D.
申请公布号 US2007168812(A1) 申请公布日期 2007.07.19
申请号 US20070655603 申请日期 2007.01.19
申请人 SUTARDJA SEHAT;AZIMI SAEED 发明人 SUTARDJA SEHAT;AZIMI SAEED
分类号 G06F11/00;G01R31/28 主分类号 G06F11/00
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