| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a synchronizing circuit wherein a setup time can be secured by flip-flops. <P>SOLUTION: In the case that there is a margin for the setup time in a flip-flop 13 in a succeeding stage, a clock signal CLK1 to be supplied to a flip-flop 12 in a preceding stage is delayed behind an output data signal DATA1 of a combinational logic circuit 21. For this purpose, a clock timing adjustment circuit 30 is provided so that the clock signal CLK1 is outputted after the data signal DATA1 is changed. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
