发明名称 CROSS-ARCHITECTURE EXECUTION OPTIMIZATION
摘要 <p>Embodiments include a device, apparatus, and a method. A device includes an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture. The device also includes a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture.</p>
申请公布号 WO2007078913(A2) 申请公布日期 2007.07.12
申请号 WO2006US48213 申请日期 2006.12.18
申请人 SEARETE LLC;FERREN, BRAN;HILLIS, DANIEL, W.;MANGIONE-SMITH, WILLIAM, HENRY;MYHRVOLD, NATHAN, P.;TEGREENE, CLARENCE, T.;WOOD, LOWELL, L., JR. 发明人 FERREN, BRAN;HILLIS, DANIEL, W.;MANGIONE-SMITH, WILLIAM, HENRY;MYHRVOLD, NATHAN, P.;TEGREENE, CLARENCE, T.;WOOD, LOWELL, L., JR.
分类号 G06F9/44 主分类号 G06F9/44
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