| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a flash EEPROM system. SOLUTION: The flash EEPROM system comprises a processor 21 and a memory system comprising an array 33 of nonvolatile floating gate memory cells divided into a plurality of sectors. The sector includes a definite group of the memory cell arrays erasable simultaneously as one unit. At least one user data section and overhead section of memory cell are provided in each sector, an address in a format for designating at least one magnetic disc sector from a processor, and the address of at least one nonvolatile memory sector corresponding to at least one magnetic disc sector is designated in response to that address.</p> |
