| 摘要 |
A configuration is provided with: memory cell arrays, sense amplifiers, bit lines that connect the memory cells and sense amplifiers, and transfer gates that are inserted on the bit lines for ON/OFF control of the connections of the memory cells and the sense amplifiers; wherein the sense-amplifier-interior bit lines, which are the sense-amplifier sides of the bit lines from the transfer gates, are arranged at positions interposed between exterior bit lines, which are the memory-cell side of the bit lines from the transfer gates.
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