发明名称 Adjustable lock-in circuit for phase-locked loops
摘要 The adjustable lock-in circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable lock-in circuits provide an adjustable initial loop condition closer to the expected loop condition according to a targeted lock-in time. In addition, the initial loop condition is varied by changing the reference voltage level.
申请公布号 US7242254(B2) 申请公布日期 2007.07.10
申请号 US20050102021 申请日期 2005.04.08
申请人 ANA SEMICONDUCTOR 发明人 PARK SANGBEOM
分类号 H03L7/00 主分类号 H03L7/00
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