| 摘要 |
A controller 102 and four flash memories F 0 to F 3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F 0 , F 1 , F 2 , F 3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F 00 , F 10 , F 01 , F 11 . Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.
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