发明名称 INTERCONNECT DELAY FAULT TEST CONTROLLER AND TEST APPARATUS USING THE SAME
摘要 An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.
申请公布号 US2007157058(A1) 申请公布日期 2007.07.05
申请号 US20060616471 申请日期 2006.12.27
申请人 KOREA ELECTRONICS TECHNOLOGY INSTITUTE 发明人 PARK CHANG W.;JEON KI M.;KIM YOUNG H.;SON JAE G.;YI HYUN B.;PARK SUNG J.
分类号 G01R31/28 主分类号 G01R31/28
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