| 摘要 |
An SRAM cell is provided to increase a noise margin of the SRAM cell by arranging a VSS line between the adjacent bit lines and thereby suppressing a capacitive coupling noise between adjacent bit lines. An SRAM cell includes an active region, first and second access gate lines, a bit line(28a), an adjacent bit line(28b), a VSS line(28c), and an access gate line connection line(30). The active region includes a first region connected with the VSS line, and second and third region where first and second access transistors are formed, respectively. The first access gate line traverses the second region, and the second access gate line traverses the third region. The bit line is connected to an end of the second region, and the adjacent bit line is connected to an end of the third region. The VSS line is arranged between the bit line and the adjacent bit line and connected to one end of the first region. The access gate line connection line couples the first and second access gate lines with each other.
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