| 摘要 |
A command control circuit for an SRAM is provided to improve operation reliability of an LCD(Liquid Crystal Display) driver by preventing a collision between a command from a CPU(Central Processing Unit) and a command for driving an LCD panel. A command control circuit for an SRAM(Static Random Access Memory) includes first and second input latches(10,20), first and second output latches(30,40), first and second timing generators(50,60), and a control block(70). The first timing generator receives a command signal from the first input latch and resets the first input and output latches after a first period. The second timing generator receives a command signal from the second input latch and resets the second input and output latches after a second period. The control block delivers the first command from the first input latch to the first output latch, delivers the second command from the second input latch to the second output latch, and resets the other output latch in response to output timing of the command signals from the first and second input latches.
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