| 摘要 |
A SRAM memory device having a common contact is provided to obtain the process margin of an activation area and a contact by applying the well isolation method to connect the activation areas of NMOS and PMOS transistors, and to unite a drain of PMOS and a contact of NMOS source. A SRAM memory device comprises an NMOS transistor and a PMOS transistor. An N-well and a P-well are formed on a silicon substrate(21). An isolation layer(22) is formed on the silicon substrate for defining an activation area. A gate is formed on the silicon substrate. A source and a drain are respectively formed in the activation area of the gate. Contacts are connected respectively with the source and the drain. The activation areas of NMOS and PMOS are interconnected, and a drain of the PMOS and a source of the NMOS are connected with a common contact(26a).
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